CGIA

CGIA = Combined GTIA and ANTIC

CGIA is a chip combining GTIA and ANTIC.

Pinout

Pin	Name	Direction	Description
1	OSC	I	Master clock input (typically 3.579 MHz)
2	S0	I	Switch I/O line 0
3	S1	I	Switch I/O line 1
4	COL	O	Color frequency ouput signal
5	S2	I	Switch I/O line 2
6	S3	I	Switch I/O line 3
7	n/c	-	not connected
8	VCC	I	Positive voltage power supply (+5.0 VDC)
9	CLUM	O	Analog video output signal
10	T0	I	Data input lines (from joystick controllers)
11	T1	I	Data input lines (from joystick controllers)
12	T2	I	Data input lines (from joystick controllers)
13	T3	I	Data input lines (from joystick controllers)
14	A0	I/O	Address bus line 0
15	A5	O	Address bus line 5
16	A6	O	Address bus line 6
17	A7	O	Address bus line 7
18	A8	I/O	Address bus line 8
19	A9	I/O	Address bus line 9
20	A10	I/O	Address bus line 10
21	A11	I/O	Address bus line 11
22	A12	I/O	Address bus line 12
23	A13	I/O	Address bus line 13
24	A14	I/O	Address bus line 14
25	A15	I/O	Address bus line 15
26	D0	I/O	Data I/O line 0
27	D1	I/O	Data I/O line 1
28	D2	I/O	Data I/O line 2
29	D3	I/O	Data I/O line 3
30	D4	I/O	Data I/O line 4
31	D5	I/O	Data I/O line 5
32	D6	I/O	Data I/O line 6
33	D7	I/O	Data I/O line 7
34	/NMI	O	Non-maskable interrupt
35	/LP	I	Signal from Lightpen
36	VSS	I	Power supply ground
37	/RNMI	I	Non-maskable interrupt
38	RDY	O	Ready
39	/REF	O	RAM refresh
40	/HALT	O	Halt
41	/RES	I	Reset
42	Φ0	O	Phase zero output for 6502 microprocessor
43	R/W	I/O	Controls direction of data transfers
44	A1	I/O	Address bus line 1
45	A2	I/O	Address bus line 2
46	A3	I/O	Address bus line 3
47	A4	I/O	Address bus line 4
48	Φ2	I	Phase two microprocessor clock from 6502 MPU